This invention relates, in general, to semiconductor devices and, more particularly, to electrically alterable, nonvolatile floating gate memory devices.
Floating gate devices, are becoming more widely used since by its nature it is nonvolatile and thus, is independent of any outside source of operating potential to maintain stored information. Further, since the devices are nonvolatile, there is neither a requirement nor a need to continuely refresh the devices and thus, there is a significant savings in power.
In a co-pending Application for Letters Patent Ser. No. 467,643 filed on 18 February 1983, entitled "DUAL WORD LINE, ELECTRICALLY ALTERABLE, NONVOLATILE FLOATING GATE MEMORY DEVICE" and now U.S. Pat. No. 4,577,215 and assigned to the same assignee as the subject application we described a novel cell wherein the capacitance C.sub.1 is formed by the interaction of the floating gate and substrate, capacitance C.sub.2 is formed by the interaction of the program line and the floating gate and, C.sub.3 is formed between the word line and the floating gate. The major thrust of our prior application was to form a nonvolatile floating gate memory device wherein the word-line-to-floating-gate capacitance is significantly greater than either the program-line-to-floating gate capacitance or the floating-gate-to-substrate capacitance. Both the program line and the word line were made to be coincident, that is they were parallel to each other and the word line was positioned above the program line. The high efficiencies were achieved by the use of the hour-glass capacitance of the floating gate and by making the program line significantly narrower than the word line. In fact, the various capacitances were proportioned to achieve the relationship: EQU C.sub.2 &lt;C.sub.3 &gt;C.sub.1 ( 1)
and that, by way of example, EQU C.sub.3 =3C.sub.2 =3C.sub.1 ( 2)
In which event, the various efficiencies would be: ##EQU1## In our cell, the word-line-to-floating-gate capacitance is made significantly greater than either the program-line-to-floating-gate capacitance or floating-gate-to-substrate capacitance thus minimizing coupling to the floating gate during a write or erase cycle in order to maximize the coupling during a read cycle.
While the device of our prior application is entirely satisfactory it is, however, felt that by rearranging the structure the device would better lend itself to more efficiently inhibiting the partial programming or smearing of adjacent cells during a "write" operation. Additionally, higher packing densities can be achieved while sacrificing little, if any, of the read and write efficiencies.